Method and structure for electrostatic discharge protection of photomasks

ABSTRACT

A mask for manufacturing integrated circuits and use of the mask. The mask has a mask substrate. The mask also has an active mask region within a first portion of the mask substrate. The active region is adapted to accumulate a pre-determined level of static electricity. The mask also has a first guard ring structure surrounding a portion of the active mask region to isolate the active region from an outer region of the mask substrate and a second guard ring structure having at least one fuse structure surrounding a portion of the first guard ring structure. The fuse structure is operably coupled to the active region to absorb a current from static electricity. The static electricity is accumulated by the active region to the pre-determined level and being discharged as current to the fuse structure while maintaining the active region free from damage from the static electricity.

CROSS-REFERENCES TO RELATED APPLICATIONS

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BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits and theirprocessing for the manufacture of semiconductor devices. Moreparticularly, the invention provides a method and device formanufacturing a mask structure including an anti-static device and arelated integrated circuit device. Merely by way of example, theinvention has been applied to guard ring structure on the mask structurefor advanced integrated circuit devices for critical masking steps. Butit would be recognized that the invention has a much broader range ofapplicability. For example, the invention can be applied to non-criticalsteps as well, as well as various interconnect structures.

Integrated circuits or “ICs” have evolved from a handful ofinterconnected devices fabricated on a single chip of silicon tomillions of devices. Current ICs provide performance and complexity farbeyond what was originally imagined. In order to achieve improvements incomplexity and circuit density (i.e., the number of devices capable ofbeing packed onto a given chip area), the size of the smallest devicefeature, also known as the device “geometry”, has become smaller witheach generation of ICs. Semiconductor devices are now being fabricatedwith features less than a quarter of a micron across.

Increasing circuit density has not only improved the complexity andperformance of ICs but has also provided lower cost parts to theconsumer. An IC fabrication facility can cost hundreds of millions, oreven billions, of dollars. Each fabrication facility will have a certainthroughput of wafers, and each wafer will have a certain number of ICson it. Therefore, by making the individual devices of an IC smaller,more devices may be fabricated on each wafer, thus increasing the outputof the fabrication facility. Making devices smaller is very challenging,as each process used in IC fabrication has a limit. That is to say, agiven process typically only works down to a certain feature size, andthen either the process or the device layout needs to be changed. Anexample of such a limit is the ability to form smaller and finerpatterns with mask structures. Such mask structures often accumulatestatic charge that discharge onto the smaller patterns to cause damageon them. Damaged masks transfer damaged patterns onto integratedcircuits, which lead to device failures and reliability problems.

Often times, damaged masks are caused by electrostatic dischargeproblems from charge that accumulates on the active region of the masks.Static charge builds up builds up to thousands of volts, which dischargefrom one region of the mask onto another region to cause damage to themask. Many attempts have been made to limit such static discharge. Asmerely an example, ionizers have been used to remove static charge fromthe masks. Other techniques include applying electrostatic dischargematerials on working surfaces of clean rooms, etc. that are used duringthe manufacture of integrated circuits with the masks. Unfortunately,human operators still handle the masks, which cause damage to the masksthemselves. Such masks often cost tens of thousands of dollars and oftenrequire a long lead-time to receive from a vendor of the mask.Accordingly, there are many limitations with conventional masks andtheir use in the manufacture of integrated circuits.

From the above, it is seen that an improved technique for processingsemiconductor devices including photo masks is desired.

BRIEF SUMMARY OF THE INVENTION

According to the present invention, techniques including methods for themanufacture of semiconductor devices are provided. More particularly,the invention provides a method and device for manufacturing a maskstructure including an anti-static device and a related integratedcircuit device. Merely by way of example, the invention has been appliedto guard ring structure on the mask structure for advanced integratedcircuit devices for critical masking steps. But it would be recognizedthat the invention has a much broader range of applicability. Forexample, the invention can be applied to non-critical steps as well, aswell as various interconnect structures.

In a specific embodiment, the invention includes a mask formanufacturing integrated circuits. The mask has a mask substrate. Themask also has an active mask region within a first portion of the masksubstrate. The active region is adapted to accumulate a pre-determinedlevel of static electricity. The mask also has a first guard ringstructure surrounding a portion of the active mask region to isolate theactive region from an outer region of the mask substrate and a secondguard ring structure having at least one fuse structure surrounding aportion of the first guard ring structure. The fuse structure isoperably coupled to the active region to absorb a current from staticelectricity. The static electricity is accumulated by the active regionto the pre-determined level and being discharged as current to the fusestructure while maintaining the active region free from damage from thestatic electricity.

In an alternative specific embodiment, the invention includes a methodfor manufacturing integrated circuit devices. The method includesreceiving a mask in a first pod. The mask includes an active region anda guard ring structure having at least one fuse structure. The methodincludes transferring the mask from the first pod into a second podwithin a clean room environment. The method includes handling the maskin the clean room environment and accumulating static electricity on themask during the handling in the clean room environment. Additionally,the method includes discharging a portion of the static charge to thefuse on the guard ring structure of the mask while maintaining theactive region of the mask free from static energy damage. The mask isused in an operation for manufacture of semiconductor integratedcircuits.

Many benefits are achieved by way of the present invention overconventional techniques. For example, the present technique provides aneasy to use process that relies upon conventional technology. In someembodiments, the method provides higher device yields in dies per wafer.Additionally, the method provides a process that is compatible withconventional process technology without substantial modifications toconventional equipment and processes. Depending upon the embodiment, oneor more of these benefits may be achieved. These and other benefits willbe described in more throughout the present specification and moreparticularly below.

Various additional objects, features and advantages of the presentinvention can be more fully appreciated with reference to the detaileddescription and accompanying drawings that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 3 are simplified top-view diagrams of conventional maskstructures;

FIGS. 4 through 7 are simplified top-view diagrams of mask structuresaccording to embodiments of the present invention; and

FIG. 8 is a simplified diagram of a method according to embodiments ofthe present invention

DETAILED DESCRIPTION OF THE INVENTION

According to the present invention, techniques including methods for themanufacture of semiconductor devices are provided. More particularly,the invention provides a method and device for manufacturing a maskstructure including an anti-static device and a related integratedcircuit device. Merely by way of example, the invention has been appliedto guard ring structure on the mask structure for advanced integratedcircuit devices for critical masking steps. But it would be recognizedthat the invention has a much broader range of applicability. Forexample, the invention can be applied to non-critical steps as well, aswell as various interconnect structures.

FIGS. 1 through 3 are simplified top-view diagrams 100, 200, 300 ofconventional mask structures and pattern on wafer. These diagrams aremerely examples, which should not unduly limit the scope of the claimsherein. One of ordinary skill in the art would recognize many othervariations, modifications, and alternatives. As shown, mask structure100 includes metal layer that define the pattern and transparent regionsurrounding the patterned metal layer. The metal can include anysuitable for blocking light. Such metal includes, but is not limited to,chrome, nickel, MoSiO₂, and Ta. Of course, the type of metal useddepends upon the application. Region 101 is a damaged region, which Idiscovered. The damaged region was caused by electrostatic dischargebetween two metal line patterns, which are close to each other. A largevoltage potential was formed between the two metal line patterns, whichshorted together via electrical current connecting the two patternstogether. The two metal patterns are 0.8 microns from each other. Thevoltage potential can be 20,000 and greater before it is discharged.

The damaged region is often from a larger pattern structure such as theone 200 in FIG. 2. Damaged region is illustrated by reference numeral201, which is between two metal line patterns. As shown, the two metalline patterns are shorted together. The metal line pattern 202 is oftenmade of a conductive material such as chrome and/or the like. Thedamaged region is transposed onto a semiconductor wafer 300 asillustrated by region 301 in FIG. 3. A more detailed diagram of thedamaged region 301 is illustrated by the simplified diagram of FIG. 3A.The damage is caused by electrostatic discharge from buildup of chargethrough a variety of production operations. Such operations include useof the mask on production equipment (e.g., robots), mask transfer pods,which house the mask for delivery, and human operators. As devicesbecome smaller, the damage caused by electrostatic discharge becomesmore serious and costly. Details of ways to overcome certain limitationsof conventional photo masks are described throughout the presentspecification and more particularly below.

FIGS. 4 through 7 are simplified top-view diagrams of mask structuresaccording to embodiments of the present invention. These diagrams aremerely examples, which should not unduly limit the scope of the claimsherein. One of ordinary skill in the art would recognize many othervariations, modifications, and alternatives. Referring to FIG. 4, maskstructure 400 includes active region 401, which is composed of patternsfor the manufacture of integrated circuits. The patterns are often foreither critical or non-critical masking steps. Examples of criticalmasking steps include 14 of 31 layers in 0.18 micron mask set. Examplesof non-critical masking steps include 17 of 31 layers. Of course,critical masking steps often require smaller tolerances thannon-critical steps.

The present mask structure also includes first anti-static guard ringstructure 403, which surrounds the periphery of the active region, onthe mask structure. The first anti-static guard ring structure serves asisolation between the active region and the second anti-static guardring structure. The first guard ring structure can be a trench region,which is filled with a dielectric layer. The trench region is free froman overlying metal layer for patterning. Referring to FIG. 5, guard ring403 is formed in the mask structure, which also includes pattern regions505, 507. The trench region is often 20 micron and less in width andalso 300 nm to about 1000 nm in thickness, depending upon theembodiment.

The mask structure also includes a second guard ring structure 405,which surrounds the periphery of the active region and the first guardring structure. The second guard ring structure includes a plurality offuse structures, which are defined spatially along the ring. Referringto FIG. 6, the second guard ring structure 405 includes the plurality offuse structures 501, which are configured in a sequential manner to formthe guard ring structure. Each of the fuse structures includes aplurality of elongated members 503, which extend to a common region 504.Each of the elongated members is a finger that has a free end. Each ofthe elongated members is substantially in parallel with anotherelongated member. Each of the members extends from metal region 507.Surrounding the metal region is insulating region 501.

Preferably, each of the fuse structures includes the free end, whichfaces an insulating region. A small gap of insulating material isdefined between the free end and conductive structure 505. Conductivestructure 505 is a region, which accumulates charge up to apredetermined level. Such predetermined level can be 20,000 volts andgreater for 1000 sized lines. Of course, the predetermined level dependsupon the application. After the predetermined level, charge traversesfrom the conductive structure through the small gap to the finger, whichacts as an antenna. Once the charge traverses through the small gap,electrostatic energy is discharged. The elongated member may connect tothe conductive structure depending upon the application.

Additionally, each of the fuse structures is provided spatially alongthe guard ring structure. Preferably, each of the structures is placedselectively adjacent to regions, which may potentially have highelectric charge accumulation. Alternatively, such structures areselectively placed and spaced in an even manner along the guard ringstructures at a predetermined frequency. Depending upon the application,there can be many modifications, alternatives, and variations. Furtherdetails of an alternative mask structure are provided throughout thepresent specification and more particularly below.

FIG. 7 is a simplified top-view diagram 700 of an alternative maskstructure according to an embodiment of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims herein. One of ordinary skill in the art would recognize manyother variations, modifications, and alternatives. As shown, the maskstructure 700 includes active region, which is composed of patterns forthe manufacture of integrated circuits. The patterns are often foreither critical or non-critical masking steps. Examples of criticalmasking steps include 14 of 31 layers in 0.18 micron mask set. Examplesof non-critical masking steps include 17 of 31 layers. Of course,critical masking steps often require smaller tolerances thannon-critical steps.

The present mask structure also includes first anti-static guard ringstructure 701, which surrounds the periphery of the active region, onthe mask structure. The first guard ring structure includes a pluralityof fuse structures, which are defined spatially along the ring. Similarto the previous embodiment, the guard ring structure includes theplurality of fuse structures 701, which are configured in a sequentialmanner to form the guard ring structure. Each of the fuse structuresincludes a plurality of elongated members, which extend from a firstregion, which connects each of the members together, to a common region.Each of the elongated members is a finger that has a free end. Each ofthe elongated members is substantially in parallel with anotherelongated member. Each of the members extends from metal region 507,which connected each of the members together. Surrounding the metalregion is insulating region.

Preferably, each of the fuse structures includes the free end, whichfaces an insulating region. A small gap of insulating material isdefined between the free end and conductive structure 505. Conductivestructure 505 is a region, which accumulates charge up to apredetermined level. Such predetermined level can be 20,000 volts andgreater for 1000 sized lines. Of course, the predetermined level dependsupon the application. After the predetermined level, charge traversesfrom the conductive structure through the small gap to the finger, whichacts as an antenna. Once the charge traverses through the small gap,electrostatic energy is discharged. The elongated member may connect tothe conductive structure depending upon the application.

A method according to an embodiment of the present invention can bebriefly provided as follows:

-   -   1. Provide mask (which has an active region and a guard ring        structure having at least one fuse structure);    -   2. Receive a mask in a first pod from a mask vendor;    -   3. Transfer the mask from the first pod into a second pod within        a clean room environment;    -   4. Handle the mask in the clean room environment;    -   5. Accumulate static electricity on one or more portions of the        mask during the handling in the clean room environment;    -   6. Continue to accumulate static electricity on the mask during        the handling in the clean room environment up to a predetermined        level;    -   7. Discharge a portion of the static electricity from the one or        more portions of the mask to one or more of the fuse structures        on the guard ring structure of the mask;    -   8. Maintain the active region of the mask free from static        energy damage as the static electricity is being discharged;    -   9. Use the mask in an operation for manufacture of semiconductor        integrated circuits; and    -   10. Continue the steps of accumulating charge and discharging        such charge onto one or more fuse structures; and    -   11. Perform other steps, as desired.

The above sequence of steps provides a method according to an embodimentof the present invention. Other alternatives can also be provided wheresteps are added, one or more steps are removed, or one or more steps areprovided in a different sequence without departing from the scope of theclaims herein. The present steps allows for static electricity to bedischarged onto a guard ring structure without causing damage to activeportions of the mask in preferred embodiments. Further details of thepresent method can be found throughout the present specification andmore particularly below.

FIG. 8 is a simplified diagram of a method 800 according to embodimentsof the present invention. These diagrams are merely examples, whichshould not unduly limit the scope of the claims herein. One of ordinaryskill in the art would recognize many other variations, modifications,and alternatives. As shown, the method begins at start, step 801. Themethod includes providing (step 803) a mask, which has an active regionand a guard ring structure having at least one fuse structure. The maskcan be similar to the ones noted above, but can also be others. Themethod receives (step 805) the mask in a first pod (e.g., mask case)from a mask vendor. Often times, the first pod is a package includingantistatic materials to dissipate any charge from the mask. The methodincludes transferring (step 807) the mask from the first pod into asecond pod within a clean room environment. The second pod is often amask SM17 pod and also has antistatic material to dissipate charge fromthe mask. Preferably, the pod is sealed, but may not be sealed.

During the manufacture of integrated circuits, the mask is handled (step809). Depending upon the application, such mask is handled by operators,handled by a robot, inspected, and stored in mask SM17 pod. Each ofthese handling processes causes electric charge via static electricityto accumulate (step 811) onto one or more portions of the activeportions of the mask. The charge accumulates and the method continuesvia branch 821 to accumulate charge on the one or more portions of themask in the clean room environment up to a predetermined level. Suchpredetermined level is often 10,000 volts, but can also be 20,000 voltsdepending upon the application. Once the mask accumulates such charge tothe predetermined level (step 813), the electric charge is dischargedand transferred (step 815) from the one or more portions of the mask toone or more of the fuse structures on the guard ring structure of themask.

Preferably, the method maintains the active region of the mask free fromstatic energy damage as the static electricity is being discharged. Themethod continues via branch 816 through a portion of the prior steps.Next, the method uses the mask in an operation for manufacture ofsemiconductor devices. Other alternatives can also be provided wheresteps are added, one or more steps are removed, or one or more steps areprovided in a different sequence without departing from the scope of theclaims herein. The present steps allows for static electricity to bedischarged onto a guard ring structure without causing damage to activeportions of the mask in preferred embodiments. The method stops at step817.

It is also understood that the examples and embodiments described hereinare for illustrative purposes only and that various modifications orchanges in light thereof will be suggested to persons skilled in the artand are to be included within the spirit and purview of this applicationand scope of the appended claims.

1. A mask for manufacturing integrated circuits, the mask comprising: amask substrate; an active mask region within a first portion of the masksubstrate, the active region being adapted to accumulate apre-determined level of static electricity; a first guard ring structuresurrounding a portion of the active mask region to isolate the activeregion from an outer region of the mask substrate; and a second guardring structure having at least one fuse structure surrounding a portionof the first guard ring structure; wherein the fuse structure isoperably coupled to the active region to absorb a current from staticelectricity, the static electricity being accumulated by the activeregion to the pre-determined level and being discharged as current tothe fuse structure while maintaining the active region free from damagefrom the static electricity.
 2. The mask of claim 1 wherein the fusestructure is a plurality of conductive regions.
 3. The mask of claim 1wherein the fuse structure has a length and a thickness.
 4. The mask ofclaim 1 wherein the fuse structure is made of a conductive material. 5.The mask of claim 1 wherein each of the fuse structures is formed on themask substrate within a predetermined distance from a portion of theactive region such that static electricity discharges to the fusestructure.
 6. The mask of claim 1 wherein the fuse structure includes aplurality of conductive members, each of the conductive membersincluding an elongated portion including a free end portion.
 7. The maskof claim 1 wherein the first guard ring structure comprises a trenchregion free from an overlying conductive layer.
 8. The mask of claim 1wherein the first guard ring structure is continuous around the activeregion to electrically and physically isolate the second guard ringstructure from the active region.
 9. The mask of claim 1 wherein thepredetermined level corresponds to a voltage no greater than 2,000,000volts.
 10. The mask of claim 1 wherein the predetermined levelcorresponds to a voltage no greater than 2,000,000 volts.
 11. A methodfor manufacturing a semiconductor integrated circuit device structurecomprising: using a mask substrate, the mask substrate comprising: anactive mask region within a first portion of the mask substrate, theactive region being adapted to accumulate a pre-determined level ofstatic electricity; a first guard ring structure surrounding a portionof the active mask region to isolate the active region from an outerregion of the mask substrate; and a second guard ring structure havingat least one fuse structure surrounding a portion of the first guardring structure; the fuse structure being operably coupled to the activeregion to absorb a current from static electricity, the staticelectricity being accumulated by the active region to the pre-determinedlevel and being discharged as current to the fuse structure whilemaintaining the active region free from damage from the staticelectricity.
 12. The method of claim 11 wherein the fuse structure is aplurality of conductive regions.
 13. The method of claim 11 wherein thefuse structures is formed on the mask substrate within a predetermineddistance from a portion of the active region such that staticelectricity discharges to the fuse structure.
 14. The method of claim 11the first guard ring structure is continuous around the active region toelectrically and physically isolate the second guard ring structure fromthe active region.
 15. The method of claim 11 wherein the fuse structureincludes a plurality of conductive members, each of the conductivemembers including an elongated portion including a free end portion. 16.The method of claim 11 wherein each of the fuse structures is formed onthe mask substrate within a predetermined distance from a portion of theactive region such that static electricity discharges to the fusestructure.
 17. A method for manufacturing integrated circuit devices,the method comprising: receiving a mask in a first pod, the maskincluding an active region and a guard ring structure having at leastone fuse structure; transferring the mask from the first pod into asecond pod within a clean room environment; handling the mask in theclean room environment; accumulating static electricity on the maskduring the handling in the clean room environment; discharging a portionof the static charge to the fuse on the guard ring structure of the maskwhile maintaining the active region of the mask free from static energydamage; and using the mask in an operation for manufacture ofsemiconductor integrated circuits.
 18. The method of claim 17 whereinthe operation is a lithography process.
 19. The method of claim 17wherein the static energy is characterized by a voltage of 1000 volts.20. The method of claim 17 wherein the static energy is characterized bya voltage of greater than 3000 volts.